1. Field of the Invention
This invention generally relates to a semiconductor device, and more particularly to a silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection.
2. Description of Related Art
As high-amplitude electrostatic discharge (ESD) pulses are an inevitable part of the daily environments, semiconductor devices are unquestionably susceptible to damages by ESD. Due to the possible occurrence of ESD during the normal lifetime of the devices, it is important that the design of the devices should provide a reasonable and acceptable level of tolerance to ESD. Typically, an additional protection structure or circuit is designed to provide a discharge path for the additional current caused during ESD, thus preventing damage to the device or the IC. ESD protection circuits or devices are usually located between the input/output (I/O) pads (or pins) and ground (or power rail). Moreover, ESD protection circuits can be incorporated into the MOS circuits on the chip.
The silicon controlled rectifier (SCR) devices have been proposed to serve as the ESD protection device due to its relatively high ESD level and small layout area. The SCR device is made up of four semiconductor layers arranged as P−N−P−N and can be considered as one PNP transistor and one NPN transistor working together. As an ESD stress having a voltage higher than the triggered point (or the turn-on voltage) is applied to the anode, the SCR device becomes conductive and permits the majority of the ESD current to bypass, thus enhancing the ESD tolerance of the circuits.
However, for the on-chip design, the parasitic capacitance of the ESD protection circuit may cause performance degradation to the core circuits of the chip. Therefore, the ESD protection circuits should be designed to minimize the parasitic capacitance for least negative impact and to sustain high enough ESD robustness for protection.